The invention relates to an integrated circuit and to a method for operating integrated circuits including identifying propagation time errors in integrated circuits.
Integrated circuits have the problem that propagation time errors occur. There is the risk that excessively fast or excessively slow signal propagation times will result in malfunctions in the integrated circuit. The higher the clock frequencies, the greater the risk of the occurrence of propagation time errors, which becomes noticeable in digital circuits from approximately 300 MHz upwards.
US 2003/0084390 exhibits a method for testing integrated circuits having different clock drivers. The flipflops in the circuit can be connected as shift registers in a scan process. In order to identify propagation time errors, data are first of all inserted into scan cells at a relatively slow clock rate in order to put the integrated circuit into a particular state. For the actual test which follows, clock pulses are generated from a PLL. The clock pulses produced in this manner are also referred to as launch/capture pulses, with the launch pulse initiating a signal which is received by using the capture pulse. To this end, clock pulses are produced whose frequency is equal to the application frequency of the integrated circuit, which allows propagation time errors to be identified.
The programming of the propagation time error test is still complex, however.
For these and other reasons, there is a need for the present invention.